Timer I/O Control Register (Tior); Table 10.11 Md3 To Md0 - Renesas H8S/2368 Series Hardware Manual

Table 10.11 MD3 to MD0

Bit 3 Bit 2 Bit 1
1 2
MD3* MD2* MD1
0 0 0
1
1 0
1
1 x x
Legend: x: Don't care
Notes: *1 MD3 is a reserved bit. The write value should always be 0.
*2 Phase counting mode cannot be set for channels 0 and 3. In this case, 0 should always
be written to MD2.
10.3.3

Timer I/O Control Register (TIOR)

TIOR registers control the TGR registers. The TPU has eight TIOR registers, two each for
channels 0 and 3, and one each for channels 1, 2, 4, and 5. Care is required since TIOR is affected
by the TMDR setting.
The initial output specified by TIOR is valid when the counter is stopped (the CST bit in TSTR is
cleared to 0). Note also that, in PWM mode 2, the output at the point at which the counter is
cleared to 0 is specified.
When TGRC or TGRD is designated for buffer operation, this setting is invalid and the register
operates as a buffer register.
Rev. 2.00, 05/03, page 386 of 820
Bit 0
MD0 Description
0 Normal operation
1 Reserved
0 PWM mode 1
1 PWM mode 2
0 Phase counting mode 1
1 Phase counting mode 2
0 Phase counting mode 3
1 Phase counting mode 4
x —