Timer I/O Control Register (Tior) - Renesas H8S Series Hardware Manual

10.3.3

Timer I/O Control Register (TIOR)

The TIOR registers are 8-bit readable/writable registers that control the TGR registers. The TPU
has eight TIOR registers, two each for channels 0 and 3, and one each for channels 1, 2, 4, and 5.
Care is required as TIOR is affected by the TMDR setting. The initial output specified by TIOR is
valid when the counter is stopped (the CST bit in TSTR is cleared to 0). Note also that, in PWM
mode 2, the output at the point at which the counter is cleared to 0 is specified.
When TGRC or TGRD is designated for buffer operation, this setting is invalid and the register
operates as a buffer register.
TIORH_0, TIOR_1, TIOR_2, TIORH_3, TIOR_4, TIOR_5
Bit Bit Name
7 IOB3
6 IOB2
5 IOB1
4 IOB0
3 IOA3
2 IOA2
1 IOA1
0 IOA0
TIORL_0, TIORL_3
Bit Bit Name
7 IOD3
6 IOD2
5 IOD1
4 IOD0
3 IOC3
2 IOC2
1 IOC1
0 IOC0
Initial
value R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
Initial
value R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
Section 10 16-Bit Timer Pulse Unit (TPU)
Description
I/O Control B0 to B3
Specify the function of TGRB.
I/O Control A0 to A3
Specify the function of TGRA.
Description
I/O Control D0 to D3
Specify the function of TGRD.
I/O Control C0 to C3
Specify the function of TGRC.
Rev. 6.00 Mar 15, 2006 page 173 of 570
REJ09B0211-0600