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M16C/64C Group
6.4.7
Oscillator Stop Detect Reset
The MCU resets and stops the pins, CPU, and SFRs when the CM27 bit in the CM2 register is 0 (reset
when oscillator stop detected), if it detects that the main clock oscillator has stopped.
The OSDR bit in the RSTFR register becomes 1 (oscillator stop detect reset detected) after oscillator
stop detect reset.
Some SFRs are not reset at oscillator stop detect reset. Refer to 4. "Special Function Registers (SFRs)"
for details. The processor mode remains unchanged since bits PM01 and PM00 in the PM0 register are
not reset.
The internal RAM is not reset. When the main clock oscillator stop is detected while writing data to the
internal RAM, the internal RAM becomes undefined.
Oscillator stop detect reset is canceled by hardware reset or voltage monitor 0 reset.
Refer to 8.7 "Oscillator Stop/Restart Detect Function" for details.
6.4.8
Watchdog Timer Reset
The MCU resets the pins, CPU, and SFRs when the PM12 bit in the PM1 register is 1 (reset when
watchdog timer underflows) and the watchdog timer underflows. Then the MCU executes the program
at the address determined by the reset vector. fOCO-S divided by 8 is automatically selected as the
CPU clock after reset.
The WDR bit in the RSTFR register becomes 1 (watchdog timer reset detected) after watchdog timer
reset. Some SFRs are not reset at watchdog timer reset. Refer to 4. "Special Function Registers
(SFRs)" for details. The processor mode remains unchanged since bits PM01 and PM00 in the PM0
register are not reset.
The internal RAM is not reset. When the watchdog timer underflows while writing data to the internal
RAM, the internal RAM becomes undefined.
Refer to 15. "Watchdog Timer" for details.
6.4.9
Software Reset
The MCU resets the pins, CPU, and SFRs when the PM03 bit in the PM0 register is 1 (MCU reset).
Then the MCU executes the program at the address determined by the reset vector. fOCO-S divided by
8 is automatically selected as the CPU clock after reset.
The SWR bit in the RSTFR register becomes 1 (software reset detected) after software reset. Some
SFRs are not reset at software reset. Refer to 4. "Special Function Registers (SFRs)" for details. The
processor mode remains unchanged since bits PM01 and PM00 in the PM0 register are not reset.
The internal RAM is not reset.
R01UH0092EJ0110 Rev.1.10
Jul 31, 2012
6. Resets
Page 56 of 807
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