Internal Reset In Watchdog Timer Mode; Ovf Flag Clearing In Intervel Timer Mode - Renesas H8S Series Hardware Manual

Section 13 Watchdog Timer
13.5.5

Internal Reset in Watchdog Timer Mode

This LSI is not reset internally if TCNT overflows while the RSTE bit is cleared to 0 during
watchdog timer operation, however TCNT and TCSR of the WDT are reset.
TCNT, TCSR, or RSTCR cannot be written to for 132 states following an overflow. During this
period, any attempt to read the WOVF flag is not acknowledged. Accordingly, wait 132 states
after overflow to write 0 to the WOVF flag for clearing.
13.5.6

OVF Flag Clearing in Intervel Timer Mode

When the OVF flag setting conflicts with the OVF flag reading in interval timer mode, writing 0
to the OVF bit may not clear the flag even though the OVF bit has been read while it is 1. If there
is a possibility that the OVF flag setting and reading will conflict, such as when the OVF flag is
polled with the intervel timer interrupt disabled, read the OVF bit while it is 1 at least twice before
writing 0 to the OVF bit to clear the flag.
Rev. 6.00 Mar 15, 2006 page 312 of 570
REJ09B0211-0600