13.3.4
Timing of Setting of Watchdog Timer Overflow Flag (WOVF)
The WOVF flag is set to 1 if TCNT overflows during watchdog timer operation. At the same time, the WDTOVF signal*
goes low. If TCNT overflows while the RSTE bit in RSTCSR is set to 1, an internal reset signal is generated for the entire
H8S/2357 Group chip. Figure 13-7 shows the timing in this case.
Note: * The WDTOVF pin function is not available in the F-ZTAT version, the H8S/2398, H8S/2394, H8S/2392, or
H8S/2390.
ø
TCNT
Overflow signal
(internal signal)
WOVF
WDTOVF signal*
Internal reset
signal
Note: * The WDTOVF pin function is not available in the F-ZTAT version, the H8S/2398, H8S/2394, H8S/2392,
or H8S/2390.
13.4
Interrupts
During interval timer mode operation, an overflow generates an interval timer interrupt (WOVI). The interval timer
interrupt is requested whenever the OVF flag is set to 1 in TCSR.
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H'FF
Figure 13-7 Timing of Setting of WOVF
H'00
132 states
518 states