Renesas H8S Series Hardware Manual page 157

8-Bit 3-State Access Space: Figure 6-7 shows the bus timing for an 8-bit 3-state access space. When an 8-bit access
space is accessed, the upper half (D
The LWR pin is fixed high. Wait states can be inserted.
Read
Write
Note: n = 0 to 7
to D ) of the data bus is used.
15 8
ø
Address bus
CSn
AS
RD
D to D
15 8
D to D
7 0
HWR
LWR
D to D
15 8
D to D
7 0
Figure 6-7 Bus Timing for 8-Bit 3-State Access Space
Bus cycle
T T
1 2
High
Valid
High impedance
T
3
Valid
Invalid
Rev.6.00 Oct.28.2004 page 129 of 1016
REJ09B0138-0600H