Renesas H8S Series Hardware Manual page 887

TSR4—Timer Status Register 4
Bit :
Initial value :
Read/Write :
Note: * Can only be written with 0 for flag clearing.
TCNT4—Timer Counter 4
Bit
Initial value
Read/Write
Note: * This timer counter can be used as an up/down-counter only in phase counting
7 6 5 4
TCFD — TCFU TCFV
1 1 0 0
R —
R/(W)* R/(W)*
Overflow Flag
0
1
Underflow Flag
0 [Clearing condition]
When 0 is written to TCFU after reading TCFU = 1
1 [Setting condition]
When the TCNT value underflows (changes from H'0000 to H'FFFF)
Count Direction Flag
0 TCNT counts down
1 TCNT counts up
: 15 14 13 12
: 0 0 0 0
: R/W R/W R/W R/W
mode or when performing overflow/underflow counting on another channel. In
other cases it functions as an up-counter.
H'FE95
3 2 1
— — TGFB
0 0 0
— — R/(W)* R/(W)*
Input Capture/Output Compare Flag A
0
1
Input Capture/Output Compare Flag B
[Clearing conditions]
0
• When DTC is activated by TGIB interrupt while DISEL
bit of MRB in DTC is 0
• When 0 is written to TGFB after reading TGFB = 1
[Setting conditions]
1
• When TCNT = TGRB while TGRB is functioning as
output compare register
• When TCNT value is transferred to TGRB by input
capture signal while TGRB is functioning as input
capture register
[Clearing condition]
When 0 is written to TCFV after reading TCFV = 1
[Setting condition]
When the TCNT value overflows (changes from H'FFFF to H'0000)
H'FE96
11 10 9 8 7
0 0 0 0 0
R/W R/W R/W R/W R/W
Up/down-counter*
TPU4
0
TGFA
0
[Clearing conditions]
• When DTC is activated by TGIA interrupt while
DISEL bit of MRB in DTC is 0
• When DMAC is activated by TGIA interrupt while
DTA bit of DMABCR in DMAC is 1
• When 0 is written to TGFA after reading TGFA = 1
[Setting conditions]
• When TCNT = TGRA while TGRA is functioning
as output compare register
• When TCNT value is transferred to TGRA by
input capture signal while TGRA is functioning
as input capture register
TPU4
6 5 4 3 2
0 0 0 0 0
R/W R/W R/W R/W R/W
Rev.6.00 Oct.28.2004 page 859 of 1016
1 0
0 0
R/W R/W
REJ09B0138-0600H