ø
A
to A
23
0
CS7 to CS0
AS
RD
(read)
D
to D
15
0
(read)
HWR, LWR
(write)
D
to D
15
0
(write)
DACK0 , DACK1
Figure 22-82 DMAC Single Address Transfer Timing (Two-State Access)
T
T
1
2
t
DACD1
t
DACD2
Rev.6.00 Oct.28.2004 page 747 of 1016
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