Register Configuration (On-Chip Rom Version Only) - Renesas H8S Series Hardware Manual

9.11.2

Register Configuration (On-Chip ROM Version Only)

Table 9-19 shows the port D register configuration.
Table 9-19 Port D Registers
Name
Port D data direction register
Port D data register
Port D register
Port D MOS pull-up control register
Note: * Lower 16 bits of the address.
Port D Data Direction Register (PDDDR) (On-Chip ROM Version Only)
Bit : 7
PD7DDR PD6DDR PD5DDR PD4DDR PD3DDR PD2DDR PD1DDR PD0DDR
Initial value : 0
R/W : W
PDDDR is an 8-bit write-only register, the individual bits of which specify input or output for the pins of port D. PDDDR
cannot be read; if it is, an undefined value will be read.
PDDDR is initialized to H'00 by a power-on reset, and in hardware standby mode. It retains its prior state after a manual
reset*, and in software standby mode.
Note: * Manual reset is only supported in the H8S/2357 ZTAT.
• Mode 7
Setting a PDDDR bit to 1 makes the corresponding port D pin an output port, while clearing the bit to 0 makes the pin
an input port.
• Modes 4 to 6
The input/output direction specification by PDDDR is ignored, and port D is automatically designated for data I/O.
Port D Data Register (PDDR) (On-Chip ROM Version Only)
Bit : 7
PD7DR
Initial value : 0
R/W : R/W
PDDR is an 8-bit readable/writable register that stores output data for the port D pins (PD
PDDR is initialized to H'00 by a power-on reset, and in hardware standby mode. It retains its prior state after a manual
reset*, and in software standby mode.
Note: * Manual reset is only supported in the H8S/2357 ZTAT.
Rev.6.00 Oct.28.2004 page 318 of 1016
REJ09B0138-0600H
6 5
0 0
W W W
6 5
PD6DR PD5DR PD4DR
0 0
R/W R/W R/W
Abbreviation R/W
PDDDR W
PDDR R/W
PORTD R
PDPCR R/W
4 3 2
0 0 0
W W
4 3 2
PD3DR PD2DR
0 0 0
R/W R/W
Initial Value Address *
H'00 H'FEBC
H'00 H'FF6C
Undefined H'FF5C
H'00 H'FF73
1 0
0 0
W W
1 0
PD1DR PD0DR
0 0
R/W R/W
to PD ).
7 0