Renesas H8S Series Hardware Manual page 987

TIOR1—Timer I/O Control Register 1
Bit :
Initial value :
Read/Write :
7 6 5
IOB3 IOB2 IOB1
0 0 0
R/W R/W R/W
TGR1B I/O Control
0 0 0 0
TGR1B Output disabled
is output
1 Initial output is
compare
0 output
register
1 0
1
1 0 0
Output disabled
1
Initial output is
1 output
1 0
1
1 0 0 0
TGR1B
Capture input
is input
source is
1
capture
TIOCB1 pin
× register
1
× ×
1
Capture input
source is TGR0C
compare match/
input capture
H'FFE2
4 3 2
IOB0 IOA3 IOA2 IOA1
0 0 0
R/W R/W R/W R/W
TGR1A I/O Control
0 0 0 0 TGR1A Output disabled
is output
Initial output is
1
compare
0 output
register
1 0
1
1 0 0 Output disabled
Initial output is
1
1 output
1 0
1
1 0 0 0 TGR1A
Capture input
is input
source is
1
capture
TIOCA1 pin
register
×
1
× ×
1 Capture input
source is TGR0A
compare match/
input capture
0 output at compare match
1 output at compare match
Toggle output at compare match
0 output at compare match
1 output at compare match
Toggle output at compare match
Input capture at rising edge
Input capture at falling edge
Input capture at both edges
Input capture at generation of
TGR0B compare match/input
capture
TPU1
1 0
IOA0
0 0
R/W
0 output at compare match
1 output at compare match
Toggle output at compare match
0 output at compare match
1 output at compare match
Toggle output at compare match
Input capture at rising edge
Input capture at falling edge
Input capture at both edges
Input capture at generation of
channel 0/TGR0A compare match/
input capture
× : Don't care
Rev.6.00 Oct.28.2004 page 959 of 1016
× : Don't care
REJ09B0138-0600H