Renesas H8S Series Hardware Manual page 434

Contention between TGR Write and Compare Match: If a compare match occurs in the T
the TGR write takes precedence and the compare match signal is inhibited. A compare match does not occur even if the
same value as before is written.
Figure 10-51 shows the timing in this case.
ø
Address
Write signal
Compare
match signal
TCNT
TGR
Contention between Buffer Register Write and Compare Match: If a compare match occurs in the T
write cycle, the data transferred to TGR by the buffer operation will be the data prior to the write.
Figure 10-52 shows the timing in this case.
ø
Address
Write signal
Compare
match signal
Buffer
register
TGR
Figure 10-52 Contention between Buffer Register Write and Compare Match
Rev.6.00 Oct.28.2004 page 406 of 1016
REJ09B0138-0600H
Figure 10-51 Contention between TGR Write and Compare Match
TGR write cycle
T T
1 2
TGR address
N N+1
N M
TGR write data
TGR write cycle
T T
1 2
Buffer register
address
N M
N
state of a TGR write cycle,
2
Prohibited
Buffer register write data
state of a TGR
2