Renesas H8S Series Hardware Manual page 213

• Block Transfer Mode
Bit 3 Bit 2
DTF3 DTF2
0 0
1
1 0
1
Note: * Detected as a low level in the first transfer after transfer is enabled.
The same factor can be selected for more than one channel. In this case, activation starts with the highest-priority channel
according to the relative channel priorities. For relative channel priorities, see section 7.5.13, DMAC Multi-Channel
Operation.
Bit 1 Bit 0
DTF1 DTF0 Description
0 0 —
1 Activated by A/D converter conversion end interrupt
Activated by DREQ pin falling edge input*
1 0
Activated by DREQ pin low-level input
1
0 0 Activated by SCI channel 0 transmission data empty
interrupt
1 Activated by SCI channel 0 reception data full interrupt
1 0 Activated by SCI channel 1 transmission data empty
interrupt
1 Activated by SCI channel 1 reception data full interrupt
0 0 Activated by TPU channel 0 compare match/input capture
A interrupt
1 Activated by TPU channel 1 compare match/input capture
A interrupt
1 0 Activated by TPU channel 2 compare match/input capture
A interrupt
1 Activated by TPU channel 3 compare match/input capture
A interrupt
0 0 Activated by TPU channel 4 compare match/input capture
A interrupt
1 Activated by TPU channel 5 compare match/input capture
A interrupt
1 0 —
1 —
(Initial value)
Rev.6.00 Oct.28.2004 page 185 of 1016
REJ09B0138-0600H