Renesas H8S Series Hardware Manual page 426

Output Compare Output Timing: A compare match signal is generated in the final state in which TCNT and TGR
match (the point at which the count value matched by TCNT is updated). When a compare match signal is generated, the
output value set in TIOR is output at the output compare output pin. After a match between TCNT and TGR, the compare
match signal is not generated until the TCNT input clock is generated.
Figure 10-36 shows output compare output timing.
ø
TCNT
input clock
TCNT
TGR
Compare
match signal
TIOC pin
Input Capture Signal Timing: Figure 10-37 shows input capture signal timing.
ø
Input capture
input
Input capture
signal
TCNT
TGR
Timing for Counter Clearing by Compare Match/Input Capture: Figure 10-38 shows the timing when counter
clearing by compare match occurrence is specified, and figure 10-39 shows the timing when counter clearing by input
capture occurrence is specified.
Rev.6.00 Oct.28.2004 page 398 of 1016
REJ09B0138-0600H
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N
Figure 10-36 Output Compare Output Timing
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Figure 10-37 Input Capture Input Signal Timing
N+1
N+1 N+2
N N+2