Programming And Verification - Renesas H8S Series Hardware Manual

19.5.2

Programming and Verification

An efficient, high-speed programming procedure can be used to program and verify PROM data. This procedure writes
data quickly without subjecting the chip to voltage stress or sacrificing data reliability. It leaves the data H'FF in unused
addresses. Figure 19-4 shows the basic high-speed programming flowchart. Tables 19-7 and 19-8 list the electrical
characteristics of the chip during programming. Figure 19-5 shows a timing chart.
No
Fail
Rev.6.00 Oct.28.2004 page 570 of 1016
REJ09B0138-0600H
Set programming/verification mode
Yes
n < 25 Program with t
No
Program with t
No go
Figure 19-4 High-Speed Programming Flowchart
Start
= 6.0 V ± 0.25 V,
V
CC
= 12.5 V ± 0.3 V
V
PP
Address = 0
n = 0
n + 1→ n
= 0.2 ms ± 5%
PW
Verification OK?
Yes
= 0.2n ms
OPW
No
Last address?
Yes
Set read mode
= 5.0 V ± 0.25 V
V
CC
V = V
PP CC
All addresses read?
Go
End
Address + 1 → address