Renesas H8S Series Hardware Manual page 468

Bit 5—Timer Overflow Flag (OVF): Status flag indicating that TCNT has overflowed (changed from H'FF to H'00).
Bit 5
OVF
0
1
Bit 4—A/D Trigger Enable (ADTE) (TCSR0 Only): Selects enabling or disabling of A/D converter start requests by
compare-match A.
In TCSR1, this bit is reserved: it is always read as 1 and cannot be modified.
Bit 4
ADTE
0
1
Bits 3 to 0—Output Select 3 to 0 (OS3 to OS0): These bits specify how the timer output level is to be changed by a
compare match of TCOR and TCNT.
Bits OS3 and OS2 select the effect of compare match B on the output level, bits OS1 and OS0 select the effect of compare
match A on the output level, and both of them can be controlled independently.
Note, however, that priorities are set such that: toggle output > 1 output > 0 output. If compare matches occur
simultaneously, the output changes according to the compare match with the higher priority.
Timer output is disabled when bits OS3 to OS0 are all 0.
After a reset, the timer output is 0 until the first compare match event occurs.
Bit 3 Bit 2
OS3 OS2
0 0
1
1 0
1
Bit 1 Bit 0
OS1 OS0
0 0
1
1 0
1
Rev.6.00 Oct.28.2004 page 440 of 1016
REJ09B0138-0600H
Description
[Clearing condition]
Cleared by reading OVF when OVF = 1, then writing 0 to OVF
[Setting condition]
Set when TCNT overflows from H'FF to H'00
Description
A/D converter start requests by compare match A are disabled
A/D converter start requests by compare match A are enabled
Description
No change when compare match B occurs
0 is output when compare match B occurs
1 is output when compare match B occurs
Output is inverted when compare match B occurs (toggle output)
Description
No change when compare match A occurs
0 is output when compare match A occurs
1 is output when compare match A occurs
Output is inverted when compare match A occurs (toggle output)
(Initial value)
(Initial value)
(Initial value)
(Initial value)