Renesas H8S Series Hardware Manual page 768

Rev.6.00 Oct.28.2004 page 740 of 1016
REJ09B0138-0600H
ø
t
AD
A to A
23 0
t
AS
t
CSD1
CS7 to CS0
AS
RD
t
AS
(read)
D to D
15 0
(read)
HWR, LWR
(write)
t
AS
D to D
15 0
(write)
Figure 22-72 Basic Bus Timing (Two-State Access)
T T
1 2
t
AH
t t
ASD ASD
t t
RSD1 ACC2
t
t
RDS
ACC3
t
t
WRD2
WRD2
t
AH
t
t t
WSW1
WDD WDH
t
RSD2
t
RDH