19.19.3 Error Protection - Renesas H8S Series Hardware Manual

19.19.3 Error Protection

In error protection, an error is detected when MCU runaway occurs during flash memory programming/erasing, or
operation is not performed in accordance with the program/erase algorithm, and the program/erase operation is aborted.
Aborting the program/erase operation prevents damage to the flash memory due to overprogramming or overerasing.
If the MCU malfunctions during flash memory programming/erasing, the FLER bit is set to 1 in FLMCR2 and the error
protection state is entered. The FLMCR1, FLMCR2, EBR1, and EBR2 settings are retained, but program mode or erase
mode is aborted at the point at which the error occurred. Program mode or erase mode cannot be re-entered by re-setting
the P or E bit. However, PV and EV bit setting is enabled, and a transition can be made to verify mode.
FLER bit setting conditions are as follows:
• When flash memory is read during programming/erasing (including a vector read or instruction fetch)
• Immediately after exception handling (excluding a reset) during programming/erasing
• When a SLEEP instruction (including software standby) is executed during programming/erasing
• When the CPU loses the bus during programming/erasing
Error protection is released only by a reset and in hardware standby mode.
Figure 19-50 shows the flash memory state transition diagram.
Normal operating mode
Program mode
Erase mode
RD VF PR ER
FLER = 0
occurrence
Error protection mode
Legend:
RD: Memory read possible
VF: Verify-read possible
PR: Programming possible
ER: Erasing possible
Rev.6.00 Oct.28.2004 page 644 of 1016
REJ09B0138-0600H
RES = 0 or STBY = 0
Error occurrence
(software standby)
Error
RD VF PR ER
FLER = 1
RD: Memory read not possible
VF: Verify-read not possible
PR: Programming not possible
ER: Erasing not possible
Figure 19-50 Flash Memory State Transitions
RES = 0 or
STBY = 0
RES = 0 or
STBY = 0
Error protection mode
Software
standby mode
Software standby
mode release
FLMCR1, FLMCR2 (except FLER
bit), EBR1, EBR2 initialization state
Reset or hardware standby
(hardware protection)
RD VF PR ER
FLER = 0
FLMCR1, FLMCR2,
EBR1, EBR2
initialization state
(software standby)
RD VF PR ER
FLER = 1