Renesas H8S Series Hardware Manual page 888

TGR4A—Timer General Register 4A
TGR4B—Timer General Register 4B
Bit
Initial value
Read/Write
TCR5—Timer Control Register 5
Bit :
Initial value :
Read/Write :
Rev.6.00 Oct.28.2004 page 860 of 1016
REJ09B0138-0600H
: 15 14 13 12
: 1 1 1 1
: R/W R/W R/W R/W R/W
7 6 5
— CCLR1 CCLR0
0 0 0
— R/W R/W
Clock Edge
Note: This setting is ignored when channel
Counter Clear
0 0 TCNT clearing disabled
1 TCNT cleared by TGRA compare match/input capture
1 0 TCNT cleared by TGRB compare match/input capture
1
TCNT cleared by counter clearing for another channel
performing synchronous clearing/synchronous operation*
Note: * Synchronous operating setting is performed by setting
the SYNC bit TSYR to 1.
H'FE98
H'FE9A
11 10 9 8 7
1 1 1 1 1
R/W R/W R/W R/W
H'FEA0
4 3 2
CKEG1 CKEG0 TPSC2
0 0 0
R/W R/W R/W
Time Prescaler
0 0 0
1
1 0
1
1 0 0
1
1 0
1
Note: This setting is ignored when channel 5 is in phase
counting mode.
0 0 Count at rising edge
1 Count at falling edge
1 — Count at both edges
5 is in phase counting mode.
TPU4
TPU4
6 5 4 3 2
1 1 1 1 1
R/W R/W R/W R/W R/W
TPU5
1 0
TPSC1 TPSC0
0 0
R/W R/W
Internal clock: counts on ø/1
Internal clock: counts on ø/4
Internal clock: counts on ø/16
Internal clock: counts on ø/64
External clock: counts on TCLKA pin input
External clock: counts on TCLKC pin input
Internal clock: counts on ø/256
External clock: counts on TCLKD pin input
1 0
1 1
R/W R/W