Pins Used For Dram Interface - Renesas H8S Series Hardware Manual

6.5.5

Pins Used for DRAM Interface

Table 6-7 shows the pins used for DRAM interfacing and their functions.
Table 6-7 DRAM Interface Pins
Pin
HWR
LCAS
CS2
CS3
CS4
CS5
CAS
WAIT
A to A
12 0
D to D
15 0
With DRAM
Setting Name
WE
Write enable
LCAS
Lower column address strobe Output Lower column address strobe
RAS2
Row address strobe 2
RAS3
Row address strobe 3
RAS4
Row address strobe 4
RAS5
Row address strobe 5
UCAS
Upper column address strobe Output Upper column address strobe
WAIT
Wait
A to A Address pins
12 0
D to D Data pins
15 0
I/O Function
Output When 2-CAS system is set,
write enable for DRAM space
access.
for 16-bit DRAM space access
Output Row address strobe when
area 2 is designated as DRAM
space.
Output Row address strobe when
area 3 is designated as DRAM
space.
Output Row address strobe when
area 4 is designated as DRAM
space.
Output Row address strobe when
area 5 is designated as DRAM
space.
for DRAM space access
Input Wait request signal
Output Row address/column address
multiplexed output
I/O Data input/output pins
Rev.6.00 Oct.28.2004 page 139 of 1016
REJ09B0138-0600H