Renesas H8S Series Hardware Manual page 357

Port F Data Register (PFDR)
Bit : 7
PF7DR
Initial value : 0
R/W : R/W
PFDR is an 8-bit readable/writable register that stores output data for the port F pins (PF
PFDR is initialized to H'00 by a power-on reset, and in hardware standby mode. It retains its prior state after a manual
reset*, and in software standby mode.
Note: * Manual reset is only supported in the H8S/2357 ZTAT.
Port F Register (PORTF)
Bit : 7
PF7
Initial value : —*
R/W : R
Note: * Determined by state of pins PF
PORTF is an 8-bit read-only register that shows the pin states. Writing of output data for the port F pins (PF
always be performed on PFDR.
If a port F read is performed while PFDDR bits are set to 1, the PFDR values are read. If a port F read is performed while
PFDDR bits are cleared to 0, the pin states are read.
After a power-on reset and in hardware standby mode, PORTF contents are determined by the pin states, as PFDDR and
PFDR are initialized. PORTF retains its prior state after a manual reset*, and in software standby mode.
Note: * Manual reset is only supported in the H8S/2357 ZTAT.
6 5
PF6DR PF5DR PF4DR
0 0
R/W R/W R/W
6 5
PF6 PF5 PF4
—* —* —*
R R
to PF .
7 0
4 3 2
PF3DR PF2DR
0 0 0
R/W R/W
4 3 2
PF3 PF2
—* —*
R R R
1 0
PF1DR PF0DR
0 0
R/W R/W
to PF ).
7 0
1 0
PF1 PF0
—* —*
R R
Rev.6.00 Oct.28.2004 page 329 of 1016
REJ09B0138-0600H
to PF ) must
7 0