Renesas H8S Series Hardware Manual page 537

• Serial data reception (clocked synchronous mode)
Figure 14-18 shows a sample flowchart for serial reception.
The following procedure should be used for serial data reception.
When changing the operating mode from asynchronous to clocked synchronous, be sure to check that the ORER, PER,
and FER flags are all cleared to 0.
The RDRF flag will not be set if the FER or PER flag is set to 1, and neither transmit nor receive operations will be
possible.
No
No
[3]
Initialization
Start reception
Read ORER flag in SSR
ORER= 1
No
Read RDRF flag in SSR
RDRF= 1
Yes
Read receive data in RDR, and
clear RDRF flag in SSR to 0
All data received?
Yes
Clear RE bit in SCR to 0
<End>
Error processing
Overrun error processing
Clear ORER flag in SSR to 0
<End>
Figure 14-18 Sample Serial Reception Flowchart
[1]
SCI initialization:
[1]
The RxD pin is automatically
designated as the receive data
input pin.
[2] [3]
[2]
If a receive error occurs, read the
ORER flag in SSR, and after
performing the appropriate error
Yes
processing, clear the ORER flag
[3]
to 0. Transfer cannot be resumed
if the ORER flag is set to 1.
Error processing
[4] SCI status check and receive
(Continued below)
data read:
Read SSR and check that the
[4]
RDRF flag is set to 1, then read
the receive data in RDR and
clear the RDRF flag to 0.
Transition of the RDRF flag from
0 to 1 can also be identified by
an RXI interrupt.
[5] Serial reception continuation
procedure:
To continue serial reception,
before the MSB (bit 7) of the
current frame is received, finish
reading the RDRF flag, reading
[5]
RDR, and clearing the RDRF flag
to 0. The RDRF flag is cleared
automatically when the DMAC or
DTC is activated by a receive
data full interrupt (RXI) request
and the RDR value is read.
Receive error processing:
Rev.6.00 Oct.28.2004 page 509 of 1016
REJ09B0138-0600H