Number Of States Required For Instruction Execution - Renesas H8S Series Hardware Manual

A.4

Number of States Required for Instruction Execution

The tables in this section can be used to calculate the number of states required for instruction execution by the CPU.
Table A-5 indicates the number of instruction fetch, data read/write, and other cycles occurring in each instruction. Table
A-4 indicates the number of states required for each cycle. The number of states required for execution of an instruction
can be calculated from these two tables as follows:
Execution states = I × S
Examples: Advanced mode, program code and stack located in external memory, on-chip supporting modules accessed in
two states with 8-bit bus width, external devices accessed in three states with one wait state and 16-bit bus width.
1. BSET #0, @FFFFC7:8
From table A-5:
I = L = 2, J = K = M = N = 0
From table A-4:
S = 4, S = 2
I L
Number of states required for execution = 2 × 4 + 2 × 2 = 12
2. JSR @@30
From table A-5:
I = J = K = 2, L = M = N = 0
From table A-4:
S = S = S = 4
I J K
Number of states required for execution = 2 × 4 + 2 × 4 + 2 × 4 = 24
Table A-4 Number of States per Cycle
Cycle
Instruction fetch
Branch address read S
Stack operation
Byte data access
Word data access
Internal operation
Legend:
m: Number of wait states inserted into external device access
Rev.6.00 Oct.28.2004 page 810 of 1016
REJ09B0138-0600H
+ J × S + K × S + L × S
I J K
On-Chip Supporting
Module
On-Chip 8-Bit
Memory Bus
S 1 4
I
J
S
K
S 2
L
S 4
M
S 1 1
N
+ M × S + N × S
L M N
Access Conditions
8-Bit Bus
16-Bit 2-State
Bus Access
2 4
2
4
1 1
External Device
16-Bit Bus
3-State 2-State 3-State
Access Access Access
6 + 2m 2 3 + m
3 + m
6 + 2m
1 1 1