Dmac Bus Cycles (Single Address Mode) - Renesas H8S Series Hardware Manual

7.5.11

DMAC Bus Cycles (Single Address Mode)

Single Address Mode (Read): Figure 7-27 shows a transfer example in which TEND output is enabled and byte-size
single address mode transfer (read) is performed from external 8-bit, 2-state access space to an external device.
Address bus
Figure 7-28 shows a transfer example in which TEND output is enabled and word-size single address mode transfer (read)
is performed from external 8-bit, 2-state access space to an external device.
ø
Address bus
RD
DACK
TEND
A one-byte or one-word transfer is performed for one transfer request, and after the transfer the bus is released. While the
bus is released, one or more bus cycles are inserted by the CPU or DTC.
In the transfer end cycle (the cycle in which the transfer counter reaches 0), a one-state DMA dead cycle is inserted after
the DMA write cycle.
Rev.6.00 Oct.28.2004 page 226 of 1016
REJ09B0138-0600H
DMA read
ø
RD
DACK
TEND
Bus Bus
release release
Figure 7-27 Example of Single Address Mode (Byte Read) Transfer
DMA read
Bus
release
Figure 7-28 Example of Single Address Mode (Word Read) Transfer
DMA read DMA read
Bus
release
DMA read
Bus
release release
DMA
DMA read
dead
Bus Last transfer Bus
release cycle release
DMA
DMA read dead
Bus Last transfer
cycle
Bus
release