Bus Control Register L (Bcrl) - Renesas H8S Series Hardware Manual

Bit 3—Burst Cycle Select 0 (BRSTS0): Selects the number of words that can be accessed in a burst ROM interface burst
access.
Bit 3
BRSTS0
0
1
Bits 2 to 0—RAM Type Select (RMTS2 to RMTS0): These bits select the memory interface for areas 2 to 5 in advanced
mode.
When DRAM space is selected, the relevant area is designated as DRAM interface.
Bit 2
RMTS2
0
1
Note: When areas selected in DRAM space are all 8-bit space, the PF
6.2.5

Bus Control Register L (BCRL)

Bit : 7
BRLE
Initial value : 0
R/W : R/W
BCRL is an 8-bit readable/writable register that performs selection of the external bus-released state protocol, the LCAS
signal, DMAC single address transfer, enabling or disabling of the write data buffer function, and enabling or disabling of
WAIT pin input.
BCRL is initialized to H'3C by a power-on reset and in hardware standby mode. It is not initialized by a manual reset* or
in software standby mode.
Note: * Manual reset is only supported in the H8S/2357 ZTAT.
Bit 7—Bus Release Enable (BRLE): Enables or disables external bus release.
Bit 7
BRLE
0
1
Rev.6.00 Oct.28.2004 page 114 of 1016
REJ09B0138-0600H
Description
Max. 4 words in burst access
Max. 8 words in burst access
Bit 1 Bit 0
RMTS1 RMTS0
0 0
1
1 0
1
— —
6 5
BREQOE EAE
0 1
R/W R/W
Description
External bus release is disabled. BREQ, BACK, and BREQO can be used as I/O ports.
External bus release is enabled.
Description
Area 5 Area 4
Normal space
Normal space
Normal space
DRAM space
—
2
4 3
LCASS DDS —
1 1
R/W R/W R/W
Area 3 Area 2
DRAM space
DRAM space
pin can be used as an I/O port, BREQO, or WAIT.
2 1 0
WDBE WAITE
1 0 0
R/W R/W
(Initial value)
(Initial value)