Pin Configuration - Renesas H8S Series Hardware Manual

6.1.3

Pin Configuration

Table 6-1 summarizes the pins of the bus controller.
Table 6-1 Bus Controller Pins
Name
Address strobe
Read
High write/write enable
Low write
Chip select 0
Chip select 1
Chip select 2/row address
strobe 2
Chip select 3/row address
strobe 3
Chip select 4/row address
strobe 4
Chip select 5/row address
strobe 5
Chip select 6
Chip select 7
Upper column address strobe
Lower column strobe
Wait
Bus request
Bus request acknowledge
Bus request output
Rev.6.00 Oct.28.2004 page 106 of 1016
REJ09B0138-0600H
Symbol I/O Function
AS
Output Strobe signal indicating that address output on
address bus is enabled.
RD
Output Strobe signal indicating that external space is
being read.
HWR
Output Strobe signal indicating that external space is to
be written, and upper half (D
enabled.
2-CAS DRAM write enable signal.
LWR
Output Strobe signal indicating that external space is to
be written, and lower half (D
enabled.
CS0
Output Strobe signal indicating that area 0 is selected.
CS1
Output Strobe signal indicating that area 1 is selected.
CS2
Output Strobe signal indicating that area 2 is selected.
DRAM row address strobe signal when area 2 is
in DRAM space.
CS3
Output Strobe signal indicating that area 3 is selected.
DRAM row address strobe signal when area 3 is
in DRAM space.
CS4
Output Strobe signal indicating that area 4 is selected.
DRAM row address strobe signal when area 4 is
in DRAM space.
CS5
Output Strobe signal indicating that area 5 is selected.
DRAM row address strobe signal when area 5 is
in DRAM space.
CS6
Output Strobe signal indicating that area 6 is selected.
CS7
Output Strobe signal indicating that area 7 is selected.
CAS
Output 2-CAS DRAM upper column address strobe
signal.
LCAS
Output DRAM lower column address strobe signal.
WAIT
Input Wait request signal when accessing external 3-
state access space.
BREQ
Input Request signal that releases bus to external
device.
BACK
Output Acknowledge signal indicating that bus has been
released.
BREQO Output
External bus request signal used when internal
bus master accesses external space when
external bus is released.
to D ) of data bus is
15 8
to D ) of data bus is
7 0