Renesas H8S Series Hardware Manual page 10

I t e m
19.18.2 Program-Verify Mode
Figure 19-48 Program/Program-
Verify Flowchart
22.3.6 Flash Memory
Characteristics
Table 22-21 Flash Memory
Characteristics (HD64F2398F20,
HD64F2398TE20)
Table 22-22 Flash Memory
Characteristics (HD64F2398F20T,
HD64F2398TE20T)
Rev.6.00 Oct.28.2004 page vi of xxiv
REJ09B0138-0600H
P a g e Revision (See Manual for Details)
639 Figure 19-48 amended, note *6 added
Write pulse application subroutine
Sub-routine write pulse
Enable WDT
Set PSU bit in FLMCR1
Wait (y) µs
Set P bit in FLMCR1
Wait (z1) µs or (z2) µs or (z3) µs
Clear P bit in FLMCR1
Wait (α) µs
Clear PSU bit in FLMCR1
Wait (β) µs
Disable WDT
End sub
Note: 7 Write Pulse Width
Write Time (z) µs
Number of Writes (n)
1 z1
2 z1
3 z1
4 z1
5 z1
6 z1
7 z2
8 z2
9 z2
10 z2
11 z2
12 z2
13 z2
. .
. .
. .
998 z2
999 z2
1000 z2
Note: Use a (z3) µs write pulse for additional
programming.
RAM
Program data area
(128 bytes)
Reprogram data area
(128 bytes)
Additional program data
area (128 bytes)
724 Table 22-21 title amended
726 Table 22-22 added
Start of programming
Start
Set SWE bit in FLMCR1
Wait (x) µs
*6 Store 128-byte program data in program
data area and reprogram data area
n = 1
*5*6
m = 0
Write 128-byte data in RAM reprogram
*6
data area consecutively to flash memory
Sub-routine-call
Write pulse
(z1) µs or (z2) µs
*6
Set PV bit in FLMCR1
Wait (γ) µs
H'FF dummy write to verify address
Wait (ε) µs
Increment address
Read verify data
Read data = verify
data?
OK
6 ≥ n ?
OK
Additional program data computation
Transfer additional program data to
additional program data area
Reprogram data computation
Transfer reprogram data to reprogram
data area
128-byte
NG
data verification
completed?
OK
Clear PV bit in FLMCR1
Wait (η) µs
6 ≥ n ?
OK
Sequentially write 128-byte data in
additional program data area in RAM to
flash memory
Write Pulse
(z3 µs additional write pulse)
m = 0?
OK
Clear SWE bit in FLMCR1
Wait (θ) µs
End of programming
Perform programming in the erased state.
Do not perform additional programming
on previously programmed addresses.
*6
*4
*1
See note 7 regarding pulse width
switching.
*6
*6
*6
n ← n + 1
*2
NG
m = 1
NG
*4
*3
*4
*6
NG
*1
*6
NG NG
n ≥ N?
OK
Clear SWE bit in FLMCR1
Wait (θ) µs
*6 *6
Programming failure