Register Descriptions (3); Dma Write Enable Register (Dmawer) - Renesas H8S Series Hardware Manual

16-bit single-chip microcomputer

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Register Descriptions (3)

The DMAC can activate the DTC with a transfer end interrupt, rewrite the channel on which the transfer ended using a

DTC chain transfer, and reactivate the DTC. DMAWER applies restrictions so that specific bits of DMACR for the

specific channel, and also DMATCR and DMABCR, can be changed to prevent inadvertent rewriting of registers other

than those for the channel concerned. The restrictions applied by DMAWER are valid for the DTC.

Figure 7-2 shows the transfer areas for activating the DTC with a channel 0A transfer end interrupt, and reactivating

channel 0A. The address register and count register area is re-set by the first DTC transfer, then the control register area is

re-set by the second DTC chain transfer.

When re-setting the control register area, perform masking by setting bits in DMAWER to prevent modification of the

contents of the other channels.

Figure 7-2 Areas for Register Re-Setting by DTC (Example: Channel 0A)

Initial value :

DMAWER is an 8-bit readable/writable register that controls enabling or disabling of writes to the DMACR, DMABCR,

and DMATCR by the DTC.

DMAWER is initialized to H'00 by a reset, and in standby mode.

Rev.6.00 Oct.28.2004 page 190 of 1016

REJ09B0138-0600H

First transfer area

Second transfer area

using chain transfer