Renesas H8S Series Hardware Manual page 217

Bits 3 and 1—Data Transfer Interrupt Enable B (DTIEB): These bits enable or disable an interrupt to the CPU or
DTC when transfer is interrupted. If the DTIEB bit is set to 1 when DTME = 0, the DMAC regards this as indicating a
break in the transfer, and issues a transfer break interrupt request to the CPU or DTC.
A transfer break interrupt can be canceled either by clearing the DTIEB bit to 0 in the interrupt handling routine, or by
performing processing to continue transfer by setting the DTME bit to 1.
Bit 3—Data Transfer Interrupt Enable 1B (DTIE1B): Enables or disables the channel 1 transfer break interrupt.
Bit 3
DTIE1B
0
1
Bit 1—Data Transfer Interrupt Enable 0B (DTIE0B): Enables or disables the channel 0 transfer break interrupt.
Bit 1
DTIE0B
0
1
Bits 2 and 0—Data Transfer End Interrupt Enable A (DTIEA): These bits enable or disable an interrupt to the CPU or
DTC when transfer ends. If DTIEA bit is set to 1 when DTE = 0, the DMAC regards this as indicating the end of a
transfer, and issues a transfer end interrupt request to the CPU or DTC.
A transfer end interrupt can be canceled either by clearing the DTIEA bit to 0 in the interrupt handling routine, or by
performing processing to continue transfer by setting the transfer counter and address register again, and then setting the
DTE bit to 1.
Bit 2—Data Transfer Interrupt Enable 1A (DTIE1A): Enables or disables the channel 1 transfer end interrupt.
Bit 2
DTIE1A
0
1
Bit 0—Data Transfer Interrupt Enable 0A (DTIE0A): Enables or disables the channel 0 transfer end interrupt.
Bit 0
DTIE0A
0
1
Description
Transfer break interrupt disabled
Transfer break interrupt enabled
Description
Transfer break interrupt disabled
Transfer break interrupt enabled
Description
Transfer end interrupt disabled
Transfer end interrupt enabled
Description
Transfer end interrupt disabled
Transfer end interrupt enabled
(Initial value)
(Initial value)
(Initial value)
(Initial value)
Rev.6.00 Oct.28.2004 page 189 of 1016
REJ09B0138-0600H