Renesas H8S Series Hardware Manual page 879

TIOR3H—Timer I/O Control Register 3H
Bit :
Initial value :
Read/Write :
7 6 5
IOB3 IOB2 IOB1
0 0 0
R/W R/W R/W
TGR3B I/O Control
0 0 0 0
TGR3B Output disabled
is output
1 Initial output is
compare
0 output
register
1 0
1
1 0 0
Output disabled
1
Initial output is 1
output
1 0
1
1 0 0 0 TGR3B Capture input
is input source is
1
capture TIOCB3 pin
register
×
1
× ×
1 Capture input
source is channel
4/count clock
Note: * If bits TPSC2 to TPSC0 in TCR4 are set to B'000, and ø/1 is used as the
TCNT4 count clock, this setting will be invalid and input capture will not
occur.
H'FE82
4 3 2
IOB0 IOA3 IOA2 IOA1
0 0 0
R/W R/W R/W R/W
TGR3A I/O Control
0 0 0 0
TGR3A Output disabled
is output
1 Initial output is
compare
0 output
register
1 0
1
1 0 0
Output disabled
1
Initial output is
1 output
1 0
1
1 TGR3A Capture input
0 0 0
is input source is
1
capture TIOCA3 pin
register
×
1
× ×
1 Capture input
source is channel
4/count clock
0 output at compare match
1 output at compare match
Toggle output at compare match
0 output at compare match
1 output at compare match
Toggle output at compare match
Input capture at rising edge
Input capture at falling edge
Input capture at both edges
Input capture at TCNT4 count-up/
*
count-down
TPU3
1 0
IOA0
0 0
R/W
0 output at compare match
1 output at compare match
Toggle output at compare match
0 output at compare match
1 output at compare match
Toggle output at compare match
Input capture at rising edge
Input capture at falling edge
Input capture at both edges
Input capture at TCNT4 count-up/
count-down
× : Don't care
Rev.6.00 Oct.28.2004 page 851 of 1016
× : Don't care
REJ09B0138-0600H