Renesas H8S Series Hardware Manual page 895

PDDDR—Port D Data Direction Register
Bit
Initial value
Read/Write
PEDDR—Port E Data Direction Register
Bit
Initial value
Read/Write
PFDDR—Port F Data Direction Register
Bit
Modes 4 to 6
Initial value
Read/Write
Mode 7
Initial value
Read/Write
PGDDR—Port G Data Direction Register
Bit
Modes 4, 5
Initial value
Read/Write
Modes 6, 7
Initial value
Read/Write
: 7 6
PD7DDR PD6DDR
: 0 0
: W W
Specify input or output for individual port D pins
:
7 6
PE7DDR PE6DDR PE5DDR
:
0 0
:
W W
Specify input or output for individual port E pins
:
7 6
PF7DDR PF6DDR
:
1 0
:
W W
:
0 0
:
W W
Specify input or output for individual port F pins
:
7 6
— —
:
Undefined Undefined
:
— —
:
Undefined Undefined
:
— —
H'FEBC
[On-chip ROM version Only]
5 4
PD5DDR PD4DDR PD3DDR
0 0
W W W
H'FEBD
5 4 3
PE4DDR PE3DDR
0 0 0
W
W W
H'FEBE
5 4
PF5DDR PF4DDR PF3DDR
0 0
W W
0 0
W W
H'FEBF
5 4
— PG4DDR PG3DDR
Undefined 1
— W W
Undefined 0
— W W
Specify input or output for individual port G pins
Port D
3 2 1
PD2DDR PD1DDR
0 0 0
W W
Port E
2 1
PE2DDR PE1DDR
0 0
W W
Port F
3 2 1
PF2DDR PF1DDR
0 0 0
W W W
0 0 0
W W W
Port G
3 2 1
PG2DDR PG1DDR
0 0 0
W W
0 0 0
W W
Rev.6.00 Oct.28.2004 page 867 of 1016
0
PD0DDR
0
W
0
PE0DDR
0
W
0
PF0DDR
0
W
0
W
0
PG0DDR
0
W
0
W
REJ09B0138-0600H