Ppg Output Mode Register (Pmr) - Renesas H8S Series Hardware Manual

Bits 3 and 2—Group 1 Compare Match Select 1 and 0 (G1CMS1, G1CMS0): These bits select the compare match
that triggers pulse output group 1 (pins PO7 to PO4).
Bit 3
G1CMS1
0
1
Bits 1 and 0—Group 0 Compare Match Select 1 and 0 (G0CMS1, G0CMS0): These bits select the compare match
that triggers pulse output group 0 (pins PO3 to PO0).
Bit 1
G0CMS1
0
1
11.2.6

PPG Output Mode Register (PMR)

Bit : 7
G3INV
Initial value : 1
R/W : R/W
PMR is an 8-bit readable/writable register that selects pulse output inversion and non-overlapping operation for each
group.
The output trigger period of a non-overlapping operation PPG output waveform is set in TGRB and the non-overlap
margin is set in TGRA. The output values change at compare match A and B.
For details, see section 11.3.4, Non-Overlapping Pulse Output.
PMR is initialized to H'F0 by a reset and in hardware standby mode. It is not initialized in software standby mode.
Bit 7—Group 3 Inversion (G3INV): Selects direct output or inverted output for pulse output group 3 (pins PO15 to
PO12).
Bit 7
G3INV
0
1
Description
Bit 2
G1CMS0 Output Trigger for Pulse Output Group 1
0 Compare match in TPU channel 0
1 Compare match in TPU channel 1
0 Compare match in TPU channel 2
1 Compare match in TPU channel 3
Description
Bit 0
G0CMS0 Output Trigger for Pulse Output Group 0
0 Compare match in TPU channel 0
1 Compare match in TPU channel 1
0 Compare match in TPU channel 2
1 Compare match in TPU channel 3
6 5
G2INV G1INV
1 1
R/W R/W
Description
Inverted output for pulse output group 3 (low-level output at pin for a 1 in PODRH)
Direct output for pulse output group 3 (high-level output at pin for a 1 in PODRH)
4 3 2
G0INV G3NOV G2NOV
1 0 0
R/W R/W R/W
(Initial value)
(Initial value)
1 0
G1NOV G0NOV
0 0
R/W R/W
(Initial value)
Rev.6.00 Oct.28.2004 page 419 of 1016
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