Renesas H8S Series Hardware Manual page 522

[b] Transmit data:
8-bit or 7-bit data is output in LSB-first order.
[c] Parity bit or multiprocessor bit:
One parity bit (even or odd parity), or one multiprocessor bit is output.
A format in which neither a parity bit nor a multiprocessor bit is output can also be selected.
[d] Stop bit(s):
One or two 1-bits (stop bits) are output.
[e] Mark state:
1 is output continuously until the start bit that starts the next transmission is sent.
[3] The SCI checks the TDRE flag at the timing for sending the stop bit.
If the TDRE flag is cleared to 0, the data is transferred from TDR to TSR, the stop bit is sent, and then serial
transmission of the next frame is started.
If the TDRE flag is set to 1, the TEND flag in SSR is set to 1, the stop bit is sent, and then the "mark state" is entered
in which 1 is output continuously. If the TEIE bit in SCR is set to 1 at this time, a TEI interrupt request is generated.
Figure 14-6 shows an example of the operation for transmission in asynchronous mode.
Start
1 bit
TDRE
TEND
TXI interrupt
request generated
Figure 14-6 Example of Operation in Transmission in Asynchronous Mode
Rev.6.00 Oct.28.2004 page 494 of 1016
REJ09B0138-0600H
Data
0 D0 D1 D7
Data written to TDR and
TDRE flag cleared to 0 in
TXI interrupt service routine
1 frame
(Example with 8-Bit Data, Parity, One Stop Bit)
Parity Stop Start
bit bit bit
0/1 1 0 D0 D1
TXI interrupt
request generated
Data Parity Stop
bit bit
Idle state
D7 0/1 1
(mark state)
TEI interrupt
request generated
1