Renesas H8S Series Hardware Manual page 912

Full address mode (cont)
:
Bit
:
DMACRB
:
Initial value
:
Read/Write
Only 0 should be
written to this bit.
Rev.6.00 Oct.28.2004 page 884 of 1016
REJ09B0138-0600H
7 6 5
— DAID DAIDE
0 0 0
R/W R/W R/W
Reserved
Only 0 should be
written to this bit.
Data Transfer Factor
DTF
3
0
1
Destination Address Increment/Decrement
0 0 MARB is fixed
1 MARB is incremented after a data transfer
1 0 MARB is fixed
1 MARB is decremented after a data transfer
4 3 2
— DTF3 DTF2
0 0 0
R/W R/W
R/W
Reserved
DTF DTF DTF
Block Transfer Mode
2 1 0
0 0 0 —
Activated by A/D converter conversion
1
end interrupt
1 0
Activated by DREQ pin falling edge input
Activated by DREQ pin low-level input
1
Activated by SCI channel 0 transmission
1 0 0
data empty interrupt
Activated by SCI channel 0 reception
1
data full interrupt
Activated by SCI channel 1 transmission
1 0
data empty interrupt
Activated by SCI channel 1 reception
1
data full interrupt
Activated by TPU channel 0 compare
0 0 0
match/input capture A interrupt
Activated by TPU channel 1 compare
1
match/input capture A interrupt
Activated by TPU channel 2 compare
1 0
match/input capture A interrupt
Activated by TPU channel 3 compare
1
match/input capture A interrupt
Activated by TPU channel 4 compare
1 0 0
match/input capture A interrupt
Activated by TPU channel 5 compare
1
match/input capture A interrupt
—
1 0
1 —
1 0
DTF1 DTF0
0 0
R/W
R/W
Normal Mode
—
—
Activated by DREQ
pin falling edge input
Activated by DREQ
pin low-level input
—
—
Auto-request (cycle
steal)
Auto-request (burst)
—
—
—
—
—
—
—
—