ø
Address bus
D
to D
Read
15
D
to D
7
HWR
Write
D
to D
15
D
to D
7
Note: n = 0 to 7
Figure 6-9 Bus Timing for 16-Bit 2-State Access Space (2) (Odd Address Byte Access)
T
CSn
AS
RD
8
0
LWR
8
0
Bus cycle
T
1
2
High
High impedance
Valid
Rev.6.00 Oct.28.2004 page 131 of 1016
Invalid
Valid
REJ09B0138-0600H