Renesas H8S Series Hardware Manual page 979

TMDR0—Timer Mode Register 0
Bit
Initial value
Read/Write
:
7 6
— —
:
1 1
:
— —
H'FFD1
5 4 3
BFB BFA MD3
0 0 0
R/W R/W R/W
Notes: 1.
TGRA Buffer Operation
0 TGRA operates normally
1
TGRA and TGRC used together
for buffer operation
TGRB Buffer Operation
0 TGRB operates normally
TGRB and TGRD used together
1
for buffer operation
TPU0
2 1
MD2 MD1
0 0
R/W R/W
Mode
0 0 0 0 Normal operation
1 Reserved
1 0 PWM mode 1
1 PWM mode 2
1 0 0 Phase counting mode 1
1 Phase counting mode 2
1 0 Phase counting mode 3
1 Phase counting mode 4
× × ×
1 —
MD3 is a reserved bit. In a write, it
should always be written with 0.
2.
Phase counting mode cannot be
set for channels 0 and 3. In this
case, 0 should always be written to
MD2.
Rev.6.00 Oct.28.2004 page 951 of 1016
0
MD0
0
R/W
× : Don't care
REJ09B0138-0600H