Renesas H8S Series Hardware Manual page 326

Port 6 Data Direction Register (P6DDR)
Bit : 7
P67DDR P66DDR P65DDR P64DDR P63DDR P62DDR P61DDR P60DDR
Initial value : 0
R/W : W
P6DDR is an 8-bit write-only register, the individual bits of which specify input or output for the pins of port 6. P6DDR
cannot be read; if it is, an undefined value will be read.
Setting a P6DDR bit to 1 makes the corresponding port 6 pin an output pin, while clearing the bit to 0 makes the pin an
input pin.
P6DDR is initialized to H'00 by a power-on reset, and in hardware standby mode. It retains its prior state after a manual
reset*, and in software standby mode. As the DMAC is initialized by a manual reset*, the pin states are determined by the
P6DDR and P6DR specifications.
Note: * Manual reset is only supported in the H8S/2357 ZTAT.
Port 6 Data Register (P6DR)
Bit : 7
P67DR
Initial value : 0
R/W : R/W
P6DR is an 8-bit readable/writable register that stores output data for the port 6 pins (P6
P6DR is initialized to H'00 by a power-on reset, and in hardware standby mode. It retains its prior state after a manual
reset*, and in software standby mode.
Note: * Manual reset is only supported in the H8S/2357 ZTAT.
Port 6 Register (PORT6)
Bit : 7
P67
Initial value : —*
R/W : R
Note: * Determined by state of pins P6
PORT6 is an 8-bit read-only register that shows the pin states. It cannot be written to. Writing of output data for the port 6
pins (P6 to P6 ) must always be performed on P6DR.
7 0
If a port 6 read is performed while P6DDR bits are set to 1, the P6DR values are read. If a port 6 read is performed while
P6DDR bits are cleared to 0, the pin states are read.
After a power-on reset and in hardware standby mode, PORT6 contents are determined by the pin states, as P6DDR and
P6DR are initialized. PORT6 retains its prior state after a manual reset*, and in software standby mode.
Note: * Manual reset is only supported in the H8S/2357 ZTAT.
Rev.6.00 Oct.28.2004 page 298 of 1016
REJ09B0138-0600H
6 5
0 0
W W W
6 5
P66DR P65DR P64DR
0 0
R/W R/W R/W
6 5
P66 P65 P64
—* —* —*
R R
to P6 .
7 0
4 3 2
0 0 0
W W
4 3 2
P63DR P62DR
0 0 0
R/W R/W
4 3 2
P63 P62
—* —*
R R R
1 0
0 0
W W
1 0
P61DR P60DR
0 0
R/W R/W
to P6 ).
7 0
1 0
P61 P60
—* —*
R R