Renesas H8S Series Hardware Manual page 64

Table 2-3 Instructions Classified by Function
Type
Data transfer
Arithmetic
operations
Rev.6.00 Oct.28.2004 page 36 of 1016
REJ09B0138-0600H
1
Instruction Size*
MOV B/W/L
MOVFPE B
MOVTPE B
POP W/L
PUSH W/L
LDM L
STM L
ADD B/W/L
SUB
ADDX B
SUBX
INC B/W/L
DEC
ADDS L
SUBS
DAA B
DAS
MULXU B/W
MULXS B/W
Function
(EAs) → Rd, Rs → (Ead)
Moves data between two general registers or between a
general register and memory, or moves immediate data
to a general register.
Cannot be used in the H8S/2357 Group.
Cannot be used in the H8S/2357 Group.
@SP+ → Rn
Pops a register from the stack. POP.W Rn is identical to
MOV.W @SP+, Rn. POP.L ERn is identical to MOV.L
@SP+, ERn.
Rn → @–SP
Pushes a register onto the stack. PUSH.W Rn is
identical to MOV.W Rn, @–SP. PUSH.L ERn is identical
to MOV.L ERn, @–SP.
@SP+ → Rn (register list)
Pops two or more general registers from the stack.
Rn (register list) → @–SP
Pushes two or more general registers onto the stack.
Rd ± Rs → Rd, Rd ± #IMM → Rd
Performs addition or subtraction on data in two general
registers, or on immediate data and data in a general
register. (Immediate byte data cannot be subtracted from
byte data in a general register. Use the SUBX or ADD
instruction.)
Rd ± Rs ± C → Rd, Rd ± #IMM ± C → Rd
Performs addition or subtraction with carry or borrow on
byte data in two general registers, or on immediate data
and data in a general register.
Rd ± 1 → Rd, Rd ± 2 → Rd
Increments or decrements a general register by 1 or 2.
(Byte operands can be incremented or decremented by
1 only.)
Rd ± 1 → Rd, Rd ± 2 → Rd, Rd ± 4 → Rd
Adds or subtracts the value 1, 2, or 4 to or from data in a
32-bit register.
Rd decimal adjust → Rd
Decimal-adjusts an addition or subtraction result in a
general register by referring to the CCR to produce 4-bit
BCD data.
Rd × Rs → Rd
Performs unsigned multiplication on data in two general
registers: either 8 bits × 8 bits → 16 bits or 16 bits ×
16 bits → 32 bits.
Rd × Rs → Rd
Performs signed multiplication on data in two general
registers: either 8 bits × 8 bits → 16 bits or 16 bits ×
16 bits → 32 bits.