Renesas H8S Series Hardware Manual page 919

ISR—IRQ Status Register
Bit
Initial value
Read/Write
Note: * Can only be written with 0 for flag clearing.
DTCERA to DTCERF—DTC Enable Registers
Bit
Initial value
Read/Write
Correspondence between Interrupt Sources and DTCER
Register 7
DTCERA IRQ0
DTCERB —
DTCERC TGI2A
DTCERD —
DTCERE DMTEND0A DMTEND0B DMTEND1A DMTEND1B RXI0
DTCERF RXI2
: 7 6
IRQ7F IRQ6F
: 0 0
: R/(W)* R/(W)*
Indicate the status of IRQ7 to IRQ0 interrupt requests
:
7 6
DTCE7 DTCE6
:
0 0
: R/W R/W
6 5
IRQ1 IRQ2
ADI TGI0A
TGI2B TGI3A
— TGI5A
TXI2 —
H'FF2F
5 4 3
IRQ5F IRQ4F IRQ3F
0 0 0
R/(W)* R/(W)* R/(W)*
H'FF30 to H'FF35
5 4 3
DTCE5 DTCE4 DTCE3
0 0 0
R/W R/W R/W
DTC Activation Enable
DTC activation by this interrupt is disabled
0 [Clearing conditions]
• When the DISEL bit is 1 and data transfer has ended
• When the specified number of transfers have ended
DTC activation by this interrupt is enabled
[Holding condition]
1
When the DISEL bit is 0 and the specified number of
transfers have not ended
Bits
4
IRQ3
TGI0B
TGI3B
TGI5B
—
Interrupt Controller
2 1
IRQ2F IRQ1F
0 0
R/(W)* R/(W)*
DTC
2 1
DTCE2 DTCE1
0 0
R/W
R/W
3 2 1
IRQ4 IRQ5 IRQ6
TGI0C TGI0D TGI1A
TGI3C TGI3D TGI4A
CMIA0 CMIB0 CMIA1
TXI0 RXI1
— — —
Rev.6.00 Oct.28.2004 page 891 of 1016
0
IRQ0F
0
R/(W)*
0
DTCE0
0
R/W
0
IRQ7
TGI1B
TGI4B
CMIB1
TXI1
—
REJ09B0138-0600H