Port G; Overview; Register Configuration - Renesas H8S Series Hardware Manual

9.14

Port G

9.14.1

Overview

Port G is a 5-bit I/O port. Port G pins also function as bus control signal output pins (CS0 to CS3, and CAS).
Figure 9-26 shows the port G pin configuration.
Port G
9.14.2

Register Configuration

Table 9-25 shows the port G register configuration.
Table 9-25 Port G Registers
Name
Port G data direction register
Port G data register
Port G register
Notes: 1. Lower 16 bits of the address.
2. Value of bits 4 to 0.
3. Initial value depends on the mode.
Rev.6.00 Oct.28.2004 page 332 of 1016
REJ09B0138-0600H
Port G pins Pin functions in mode 7*
PG
PG / CS0
4
4
PG
PG / CS1
3
3
PG
PG / CS2
2
2
PG
PG / CS3
1
1
PG
PG / CAS
0
0
Note: * Modes 6 and 7 are provided in the on-chip ROM version only.
Figure 9-26 Port G Pin Functions
Abbreviation
PGDDR
PGDR
PORTG
Pin functions in modes 4 to 6*
(I/O) PG
(I/O) PG
(I/O) PG
PG
(I/O)
PG
(I/O)
R/W Initial Value*
W H'10/H'00*
R/W H'00
R Undefined
(input)/CS0 (output)
4
(input)/CS1 (output)
3
(input)/CS2 (output)
2
(input)/CS3 (output)
1
(I/O)/CAS (output)
0
2
Address*
3
H'FEBF
H'FF6F
H'FF5F
1