Renesas H8S Series Hardware Manual page 161

16-Bit 3-State Access Space: Figures 6-11 to 6-13 show bus timings for a 16-bit 3-state access space. When a 16-bit
access space is accessed , the upper half (D
D ) for the odd address.
0
Wait states can be inserted.
Read
Write
Note: n = 0 to 7
Figure 6-11 Bus Timing for 16-Bit 3-State Access Space (1) (Even Address Byte Access)
to D ) of the data bus is used for the even address, and the lower half (D
15 8
ø
Address bus
CSn
AS
RD
D to D
15 8
D to D
7 0
HWR
LWR
D to D
15 8
D to D
7 0
Bus cycle
T T
1 2
High
Valid
High impedance
T
3
Valid
Invalid
Rev.6.00 Oct.28.2004 page 133 of 1016
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