Renesas H8S Series Hardware Manual page 901

BCRL—Bus Control Register L
Bit
Initial value
Read/Write
Bus Release Enable
0
1
: 7 6 5
BRLE BREQOE EAE
: 0 0 1
: R/W R/W R/W
LCAS Select
Write 0 to this bit when using the DRAM interface
External Addresses H'010000 to H'01FFFF *
0 On-chip ROM
1 External addresses (in external expansion mode)
or reserved area *
Notes: 1. External addresses H'010000 to H'01FFFF for the H8S/2357
External addresses H'010000 to H'03FFFF for the H8S/2398
2. Do not access a reserved area.
BREQO Pin Enable
0 BREQO output disabled
1 BREQO output enabled
External bus release is disabled
External bus release is enabled
H'FED5
4 3 2
LCASS DDS —
1 1 1
R/W R/W R/W
WAIT Pin Enable
0
1
Write Data Buffer Enable
0
Write data buffer function not used
1 Write data buffer function used
Reserved
Only 1 should be written to this bit
DACK Timing Select
When DMAC single address transfer is performed in
0 DRAM/PSRAM space, full access is always executed
DACK signal goes low from T
Burst access is possible when DMAC single address
1
transfer is performed in DRAM/PSRAM space
DACK signal goes low from T
1
Enable
2
(in single-chip mode)
Bus Controller
1 0
WDBE WAITE
0 0
R/W R/W
Wait input by WAIT pin disabled
Wait input by WAIT pin enabled
or T cycle
r 1
or T cycle
c1 2
Rev.6.00 Oct.28.2004 page 873 of 1016
REJ09B0138-0600H