Renesas H8S/2300 Series Manuals

Manuals and User Guides for Renesas H8S/2300 Series. We have 2 Renesas H8S/2300 Series manuals available for free PDF download: Hardware Manual

Renesas H8S/2300 Series Hardware Manual (875 pages)

16-Bit Single-Chip Microcomputer

Brand: Renesas | Category: Computer Hardware | Size: 5.48 MB

Renesas H8S/2300 Series Hardware Manual (1047 pages)

16-Bit Single-Chip Microcomputer

Brand: Renesas | Category: Computer Hardware | Size: 4.54 MB

Table of Contents
13
Section 1 Overview

29
- Overview
  29
- Block Diagram
  34
- Pin Description
  35
  - Pin Arrangement
    35
  - Pin Functions in each Operating Mode
    39
  - Pin Functions
    43
Section 2 CPU

49
- Overview
  49
- CPU Operating Modes
  51
  - Advanced Mode
    51
- Address Space
  54
- Register Configuration
  55
  - Overview
    55
  - General Registers
    55
  - Control Registers
    56
  - Initial Register Values
    57
- Data Formats
  58
  - General Register Data Formats
    58
  - Memory Data Formats
    60
- Instruction Set
  61
- Addressing Modes and Effective Address Calculation
  69
  - Addressing Mode
    69
  - Effective Address Calculation
    72
- Processing States
  75
  - Overview
    75
  - Reset State
    76
  - Exception-Handling State
    76
  - Program Execution State
    78
  - Bus-Released State
    78
  - Power-Down State
    78
- Basic Timing
  79
- Usage Note
  81
  - TAS Instruction
    81
Section 3 MCU Operating Modes

83
Section 4 Exception Handling

99
- Overview
  99
- Reset
  102
  - Overview
    102
  - Reset Types
    102
  - Reset Sequence
    103
  - Interrupts after Reset
    104
  - State of On-Chip Supporting Modules after Reset Release
    104
- Traces
  104
- Interrupts
  105
- Trap Instruction
  106
- Stack Status after Exception Handling
  106
- Notes on Use of the Stack
  107
Section 5 Interrupt Controller

109
- Overview
  109
  - Features
    109
  - Block Diagram
    110
  - Pin Configuration
    110
  - Register Configuration
    111
- Register Descriptions
  111
- Interrupt Sources
  115
  - External Interrupts
    115
  - Internal Interrupts
    116
  - Interrupt Exception Handling Vector Table
    116
- Interrupt Operation
  119
  - Interrupt Control Modes and Interrupt Operation
    119
  - Interrupt Control Mode 0
    121
  - Interrupt Control Mode 2
    123
  - Interrupt Exception Handling Sequence
    125
  - Interrupt Response Times
    126
- Usage Notes
  127
- DTC and DMAC Activation by Interrupt
  128
  - Overview
    128
  - Block Diagram
    129
  - Operation
    129
  - Note on Use
    130
Section 6 Bus Controller

131
- Overview
  131
  - Features
    131
  - Block Diagram
    133
  - Pin Configuration
    134
  - Register Configuration
    135
- Register Descriptions
  136
- Overview of Bus Control
  149
  - Area Partitioning
    149
  - Bus Specifications
    150
  - Memory Interfaces
    151
  - Advanced Mode
    151
  - Chip Select Signals
    152
- Basic Bus Interface
  153
  - Overview
    153
  - Data Size and Data Alignment
    153
  - Valid Strobes
    155
  - Basic Timing
    156
  - Wait Control
    164
- DRAM Interface
  166
  - Overview
    166
  - Setting DRAM Space
    166
  - Address Multiplexing
    166
  - Data Bus
    166
  - Pins Used for DRAM Interface
    167
  - Basic Timing
    168
  - Precharge State Control
    169
  - Wait Control
    169
  - Byte Access Control
    171
  - Burst Operation
    172
  - Refresh Control
    175
- DMAC Single Address Mode and DRAM Interface
  177
  - When DDS = 1
    177
  - When DDS = 0
    178
- Burst ROM Interface
  178
  - Overview
    178
  - Basic Timing
    179
  - Wait Control
    180
- Idle Cycle
  181
  - Operation
    181
  - Usage Notes
    183
  - Pin States in Idle Cycle
    185
- Write Data Buffer Function
  186
- Bus Release
  187
  - Overview
    187
  - Operation
    187
  - Pin States in External Bus Released State
    188
  - Transition Timing
    189
  - Usage Note
    189
- Bus Arbitration
  190
  - Overview
    190
  - Operation
    190
  - Bus Transfer Timing
    191
  - External Bus Release Usage Note
    191
- Resets and the Bus Controller
  192
Section 7 DMA Controller

193
- Overview
  193
  - Features
    193
  - Block Diagram
    194
  - Overview of Functions
    195
  - Pin Configuration
    197
  - Register Configuration
    198
- Register Descriptions (1) (Short Address Mode)
  199
  - Memory Address Registers (MAR)
    200
  - I/O Address Register (IOAR)
    200
  - Execute Transfer Count Register (ETCR)
    201
  - DMA Control Register (DMACR)
    202
  - DMA Band Control Register (DMABCR)
    205
- Register Descriptions (2) (Full Address Mode)
  209
  - Memory Address Register (MAR)
    209
  - I/O Address Register (IOAR)
    209
  - Execute Transfer Count Register (ETCR)
    209
  - DMA Control Register (DMACR)
    211
  - DMA Band Control Register (DMABCR)
    214
- Register Descriptions (3)
  218
- Operation
  222
  - Transfer Modes
    222
  - Sequential Mode
    224
  - Idle Mode
    227
  - Repeat Mode
    229
  - Single Address Mode
    232
  - Normal Mode
    235
  - Block Transfer Mode
    238
  - DMAC Activation Sources
    243
  - Basic DMAC Bus Cycles
    245
  - DMAC Bus Cycles (Dual Address Mode)
    246
  - DMAC Bus Cycles (Single Address Mode)
    254
  - Write Data Buffer Function
    258
  - DMAC Multi-Channel Operation
    259
  - Relation between External Bus Requests, Refresh Cycles, the DTC, and the DMAC
    260
  - NMI Interrupts and DMAC
    261
  - Forced Termination of DMAC Operation
    262
  - Clearing Full Address Mode
    263
- Interrupts
  264
- Usage Notes
  265
Section 8 Data Transfer Controller

269
- Overview
  269
  - Features
    269
  - Block Diagram
    270
  - Register Configuration
    271
- Register Descriptions
  272
  - DTC Mode Register a (MRA)
    272
  - DTC Mode Register B (MRB)
    273
  - DTC Source Address Register (SAR)
    274
  - DTC Destination Address Register (DAR)
    274
  - DTC Transfer Count Register a (CRA)
    274
  - DTC Transfer Count Register B (CRB)
    274
  - DTC Enable Registers (DTCER)
    275
  - DTC Vector Register (DTVECR)
    275
  - Module Stop Control Register (MSTPCR)
    276
- Operation
  277
  - Overview
    277
  - Activation Sources
    279
  - DTC Vector Table
    280
  - Location of Register Information in Address Space
    283
  - Normal Mode
    284
  - Repeat Mode
    285
  - Block Transfer Mode
    286
  - Chain Transfer
    287
  - Operation Timing
    288
  - Number of DTC Execution States
    289
  - Procedures for Using DTC
    290
  - Examples of Use of the D7TC
    290
- Interrupts
  292
- Usage Notes
  292
Section 9 I/O Ports

293
- Overview
  293
- Port1
  297
  - Overview
    297
  - Register Configuration
    297
  - Pin Functions
    299
- Port2
  307
  - Overview
    307
  - Register Configuration
    307
  - Pin Functions
    309
- Port 3
  317
  - Overview
    317
  - Register Configuration
    317
  - Pin Functions
    319
- Port 4
  321
  - Overview
    321
  - Register Configuration
    321
  - Pin Functions
    321
- Port 5
  322
  - Overview
    322
  - Register Configuration
    322
  - Pin Functions
    324
- Port 6
  325
  - Overview
    325
  - Register Configuration
    325
  - Pin Functions
    327
- Port a
  329
  - Overview
    329
  - Register Configuration
    330
  - Pin Functions
    332
  - MOS Input Pull-Up Function (On-Chip ROM Version Only)
    334
- Port B
  335
  - Overview
    335
  - Register Configuration (On-Chip ROM Version Only)
    336
  - Pin Functions
    338
  - MOS Input Pull-Up Function (On-Chip ROM Version Only)
    339
- Port C
  340
  - Overview
    340
  - Register Configuration (On-Chip ROM Version Only)
    341
  - Pin Functions
    343
  - MOS Input Pull-Up Function (On-Chip ROM Version Only)
    344
- Port D
  345
  - Overview
    345
  - Register Configuration (On-Chip ROM Version Only)
    346
  - Pin Functions
    348
  - MOS Input Pull-Up Function (On-Chip ROM Version Only)
    349
- Port E
  350
  - Overview
    350
  - Register Configuration
    351
  - Pin Functions
    353
  - MOS Input Pull-Up Function (On-Chip ROM Version Only)
    354
- Port F
  355
  - Overview
    355
  - Register Configuration
    356
  - Pin Functions
    358
- Port G
  360
  - Overview
    360
  - Register Configuration
    360
  - Pin Functions
    363
Section 10 16-Bit Timer Pulse Unit (TPU)

365
- Overview
  365
  - Features
    365
  - Block Diagram
    369
  - Pin Configuration
    370
  - Register Configuration
    371
- Register Descriptions
  373
  - Timer Control Register (TCR)
    373
  - Timer Mode Register (TMDR)
    377
  - Timer I/O Control Register (TIOR)
    379
  - Timer Interrupt Enable Register (TIER)
    389
  - Timer Status Register (TSR)
    391
  - Timer Counter (TCNT)
    394
  - Timer General Register (TGR)
    394
  - Timer Start Register (TSTR)
    394
  - Timer Synchro Register (TSYR)
    395
  - Module Stop Control Register (MSTPCR)
    396
- Interface to Bus Master
  397
  - 16-Bit Registers
    397
  - 8-Bit Registers
    398
- Operation
  399
  - Overview
    399
  - Basic Functions
    400
  - Synchronous Operation
    405
  - Buffer Operation
    407
  - Cascaded Operation
    410
  - PWM Modes
    411
  - Phase Counting Mode
    416
- Interrupts
  422
  - Interrupt Sources and Priorities
    422
  - DTC/DMAC Activation
    424
  - A/D Converter Activation
    424
- Operation Timing
  425
  - Input/Output Timing
    425
  - Interrupt Signal Timing
    429
- Usage Notes
  432

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Renesas H8S/2300 Series Manuals

Renesas H8S/2300 Series Hardware Manual (875 pages)

Table of Contents

Renesas H8S/2300 Series Hardware Manual (1047 pages)

Table of Contents

Section 1 Overview

Section 2 CPU

Section 3 MCU Operating Modes

Section 4 Exception Handling

Section 5 Interrupt Controller

Section 6 Bus Controller

Section 7 DMA Controller

Section 8 Data Transfer Controller

Section 9 I/O Ports

Section 10 16-Bit Timer Pulse Unit (TPU)

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