Block Diagram - Renesas H8S Series Hardware Manual

10.1.2

Block Diagram

Figure 10-1 shows a block diagram of the TPU.
Input/output pins
Channel 3: TIOCA3
TIOCB3
TIOCC3
TIOCD3
Channel 4: TIOCA4
TIOCB4
Channel 5: TIOCA5
TIOCB5
Clock input
Internal clock:
ø/1
ø/4
ø/16
ø/64
ø/256
ø/1024
ø/4096
External clock:
TCLKA
TCLKB
TCLKC
TCLKD
Input/output pins
Channel 0: TIOCA0
TIOCB0
TIOCC0
TIOCD0
Channel 1: TIOCA1
TIOCB1
Channel 2: TIOCA2
TIOCB2
Figure 10-1 Block Diagram of TPU
Interrupt request signals
Channel 3: TGI3A
TGI3B
TGI3C
TGI3D
TCI3V
Channel 4: TGI4A
TGI4B
TCI4V
TCI4U
Channel 5: TGI5A
TGI5B
TCI5V
TCI5U
Internal data bus
A/D conversion start request signal
PPG output trigger signal
Interrupt request signals
Channel 0: TGI0A
TGI0B
TGI0C
TGI0D
TCI0V
Channel 1: TGI1A
TGI1B
TCI1V
TCI1U
Channel 2: TGI2A
TGI2B
TCI2V
TCI2U
Rev.6.00 Oct.28.2004 page 341 of 1016
REJ09B0138-0600H