Timer Control/Status Registers 0 And 1 (Tcsr0, Tcsr1) - Renesas H8S Series Hardware Manual

12.2.5

Timer Control/Status Registers 0 and 1 (TCSR0, TCSR1)

TCSR0
Bit : 7
CMFB
Initial value : 0
R/W : R/(W)*
TCSR1
Bit : 7
CMFB
Initial value : 0
R/W : R/(W)*
Note: * Only 0 can be written to bits 7 to 5, to clear these flags.
TCSR0 and TCSR1 are 8-bit registers that display compare match and overflow statuses, and control compare match
output.
TCSR0 is initialized to H'00, and TCSR1 to H'10, by a reset and in hardware standby mode.
Bit 7—Compare Match Flag B (CMFB): Status flag indicating whether the values of TCNT and TCORB match.
Bit 7
CMFB
0
1
Bit 6—Compare Match Flag A (CMFA): Status flag indicating whether the values of TCNT and TCORA match.
Bit 6
CMFA
0
1
6 5
CMFA OVF
0 0
R/(W)* R/(W)*
6 5
CMFA OVF
0 0
R/(W)* R/(W)*
Description
[Clearing conditions]
•
Cleared by reading CMFB when CMFB = 1, then writing 0 to CMFB
•
When DTC is activated by CMIB interrupt while DISEL bit of MRB in DTC is 0
[Setting condition]
Set when TCNT matches TCORB
Description
[Clearing conditions]
•
Cleared by reading CMFA when CMFA = 1, then writing 0 to CMFA
•
When DTC is activated by CMIA interrupt while DISEL bit of MRB in DTC is 0
[Setting condition]
Set when TCNT matches TCORA
4 3 2
ADTE OS3 OS2
0 0 0
R/W R/W R/W
4 3 2
— OS3 OS2
1 0 0
— R/W R/W
1 0
OS1 OS0
0 0
R/W R/W
1 0
OS1 OS0
0 0
R/W R/W
(Initial value)
(Initial value)
Rev.6.00 Oct.28.2004 page 439 of 1016
REJ09B0138-0600H