Renesas H8S Series Hardware Manual page 14

Section 3 MCU Operating Modes ......................................................................................................55
3.1 Overview..................................................................................................................................................................... 55
3.1.1 Operating Mode Selection (H8S/2357 F-ZTAT Only) ................................................................................. 55
3.1.2 Operating Mode Selection (ZTAT, Masked ROM, ROMless Version, and H8S/2398 F-ZTAT) ............... 56
3.1.3 Register Configuration ..................................................................................................................................57
3.2 Register Descriptions..................................................................................................................................................57
3.2.1 Mode Control Register (MDCR)................................................................................................................... 57
3.2.2 System Control Register (SYSCR) ............................................................................................................... 57
3.2.3 System Control Register 2 (SYSCR2) (F-ZTAT Version Only) ..................................................................58
3.3 Operating Mode Descriptions..................................................................................................................................... 60
3.3.1 Mode 1........................................................................................................................................................... 60
3.3.2 Mode 2 (H8S/2398 F-ZTAT Only) ............................................................................................................... 60
3.3.3 Mode 3 (H8S/2398 F-ZTAT Only) ............................................................................................................... 60
3.3.4 Mode 4 (On-Chip ROM Disabled Expansion Mode) ................................................................................... 60
3.3.5 Mode 5 (On-Chip ROM Disabled Expansion Mode) ................................................................................... 60
3.3.6 Mode 6 (On-Chip ROM Enabled Expansion Mode)..................................................................................... 60
3.3.7 Mode 7 (Single-Chip Mode) ......................................................................................................................... 61
3.3.8 Modes 8 and 9 ............................................................................................................................................... 61
3.3.9 Mode 10 (H8S/2357 F-ZTAT Only) ............................................................................................................. 61
3.3.10 Mode 11 (H8S/2357 F-ZTAT Only) ............................................................................................................. 61
3.3.11 Modes 12 and 13 (H8S/2357 F-ZTAT Only)................................................................................................61
3.3.12 Mode 14 (H8S/2357 F-ZTAT Only) ............................................................................................................. 61
3.3.13 Mode 15 (H8S/2357 F-ZTAT Only)............................................................................................................. 61
3.4 Pin Functions in Each Operating Mode......................................................................................................................62
3.5 Memory Map in Each Operating Mode......................................................................................................................62
Section 4 Exception Handling ............................................................................................................71
4.1 Overview..................................................................................................................................................................... 71
4.1.1 Exception Handling Types and Priority ........................................................................................................71
4.1.2 Exception Handling Operation ......................................................................................................................72
4.1.3 Exception Vector Table................................................................................................................................. 72
4.2 Reset ........................................................................................................................................................................... 74
4.2.1 Overview ....................................................................................................................................................... 74
4.2.2 Reset Types ................................................................................................................................................... 74
4.2.3 Reset Sequence..............................................................................................................................................75
4.2.4 Interrupts after Reset ..................................................................................................................................... 76
4.2.5 State of On-Chip Supporting Modules after Reset Release ..........................................................................76
4.3 Traces ......................................................................................................................................................................... 76
4.4 Interrupts..................................................................................................................................................................... 77
4.5 Trap Instruction ..........................................................................................................................................................78
4.6 Stack Status after Exception Handling ....................................................................................................................... 78
4.7 Notes on Use of the Stack........................................................................................................................................... 79
Section 5 Interrupt Controller.............................................................................................................81
5.1 Overview..................................................................................................................................................................... 81
5.1.1 Features ......................................................................................................................................................... 81
5.1.2 Block Diagram............................................................................................................................................... 82
5.1.3 Pin Configuration ..........................................................................................................................................82
5.1.4 Register Configuration ..................................................................................................................................83
5.2 Register Descriptions..................................................................................................................................................83
5.2.1 System Control Register (SYSCR) ............................................................................................................... 83
Rev.6.00 Oct.28.2004 page x of xxiv
REJ09B0138-0600H