Dma Control Register (Dmacr) - Renesas H8S Series Hardware Manual

7.3.4

DMA Control Register (DMACR)

DMACR is a 16-bit readable/writable register that controls the operation of each DMAC channel. In full address mode,
DMACRA and DMACRB have different functions.
DMACR is initialized to H'0000 by a reset, and in hardware standby mode.
DMACRA
Bit : 15
DMACRA : DTSZ
Initial value : 0
R/W : R/W
DMACRB
Bit : 7
DMACRB : —
Initial value : 0
R/W : R/W
Bit 15—Data Transfer Size (DTSZ): Selects the size of data to be transferred at one time.
Bit 15
DTSZ
0
1
Bit 14—Source Address Increment/Decrement (SAID)
Bit 13—Source Address Increment/Decrement Enable (SAIDE): These bits specify whether source address register
MARA is to be incremented, decremented, or left unchanged, when data transfer is performed.
Bit 14
SAID
0
1
Bit 12—Block Direction (BLKDIR)
14 13
SAID SAIDE
0 0
R/W R/W
6 5
DAID DAIDE
0 0
R/W R/W
Description
Byte-size transfer
Word-size transfer
Bit 13
SAIDE Description
0 MARA is fixed
1 MARA is incremented after a data transfer
•
When DTSZ = 0, MARA is incremented by 1 after a transfer
•
When DTSZ = 1, MARA is incremented by 2 after a transfer
0 MARA is fixed
1 MARA is decremented after a data transfer
•
When DTSZ = 0, MARA is decremented by 1 after a transfer
•
When DTSZ = 1, MARA is decremented by 2 after a transfer
12 11
BLKDIR BLKE
0 0
R/W R/W R/W
4 3
— DTF3 DTF2
0 0
R/W R/W R/W
10 9 8
— — —
0 0 0
R/W R/W
2 1 0
DTF1 DTF0
0 0 0
R/W R/W
Rev.6.00 Oct.28.2004 page 183 of 1016
(Initial value)
(Initial value)
REJ09B0138-0600H