System Control Register 2 (Syscr2); Ram Emulation Register (Ramer) - Renesas H8S Series Hardware Manual

16-bit single-chip microcomputer

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System Control Register 2 (SYSCR2)

Initial value

SYSCR2 is an 8-bit readable/writable register that controls on-chip flash memory (in F-ZTAT versions).

SYSCR2 is initialized to H'00 by a reset and in hardware standby mode.

SYSCR2 is available only in the F-ZTAT version. In the masked ROM and ZTAT versions, this register cannot be

written to and will return an undefined value if read.

Bits 7 to 4—Reserved: These bits cannot be modified and are always read as 0.

Bit 3—Flash Memory Control Register Enable (FLSHE): Controls CPU access to the flash memory control registers

(FLMCR1, FLMCR2, EBR1, and EBR2). Setting the FLSHE bit to 1 enables read/write access to the flash memory

control registers. If FLSHE is cleared to 0, the flash memory control registers are deselected. In this case, the flash

memory control register contents are retained.

Bits 2 to 0—Reserved: These bits cannot be modified and are always read as 0.

RAMER specifies the area of flash memory to be overlapped with part of RAM when emulating real-time flash memory

programming. RAMER is initialized to H'00 by a reset and in hardware standby mode. It is not initialized in software

standby mode. RAMER settings should be made in user mode or user program mode.

Flash memory area divisions are shown in table 19-13. To ensure correct operation of the emulation function, the ROM

for which RAM emulation is performed should not be accessed immediately after this register has been modified. Normal

execution of an access immediately after register modification is not guaranteed.

Initial value:

Bits 7 to 3—Reserved: These bits are always read as 0.

Rev.6.00 Oct.28.2004 page 586 of 1016

REJ09B0138-0600H

Flash control registers deselected in area H'FFFFC8 to H'FFFFCB

Flash control registers selected in area H'FFFFC8 to H'FFFFCB

(Initial value)