Renesas H8S Series Hardware Manual page 375

Bits 4 and 3—Clock Edge 1 and 0 (CKEG1, CKEG0): These bits select the input clock edge. When the input clock is
counted using both edges, the input clock period is halved (e.g. ø/4 both edges = ø/2 rising edge). If phase counting mode
is used on channels 1, 2, 4, and 5, this setting is ignored and the phase counting mode setting has priority.
Bit 4
CKEG1
0
1
Note: Internal clock edge selection is valid when the input clock is ø/4 or slower. This setting is ignored if the input clock is
ø/1, or when overflow/underflow of another channel is selected.
Bits 2 to 0—Time Prescaler 2 to 0 (TPSC2 to TPSC0): These bits select the TCNT counter clock. The clock source can
be selected independently for each channel. Table 10-4 shows the clock sources that can be set for each channel.
Table 10-4 TPU Clock Sources
Channel ø/1
0
1
2
3
4
5
Legend:
: Setting
Blank: No setting
Channel
0
Bit 3
CKEG0 Description
0 Count at rising edge
1 Count at falling edge
— Count at both edges
Internal Clock
ø/4 ø/16 ø/64 ø/256 ø/1024 ø/4096
Bit 2 Bit 1
TPSC2 TPSC1
0 0
1
1 0
1
TCLKA TCLKB TCLKC TCLKD Channel
Bit 0
TPSC0 Description
0 Internal clock: counts on ø/1
1 Internal clock: counts on ø/4
0 Internal clock: counts on ø/16
1 Internal clock: counts on ø/64
0 External clock: counts on TCLKA pin input
1 External clock: counts on TCLKB pin input
0 External clock: counts on TCLKC pin input
1 External clock: counts on TCLKD pin input
(Initial value)
Overflow/
Underflow
External Clock
on Another
(Initial value)
Rev.6.00 Oct.28.2004 page 347 of 1016
REJ09B0138-0600H