Renesas H8S Series Hardware Manual page 412

16-bit single-chip microcomputer

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PWM output is generated from the TIOCA and TIOCC pins by pairing TGRA with TGRB and TGRC with TGRD.

The output specified by bits IOA3 to IOA0 and IOC3 to IOC0 in TIOR is output from the TIOCA and TIOCC pins at

compare matches A and C, and the output specified by bits IOB3 to IOB0 and IOD3 to IOD0 in TIOR is output at

compare matches B and D. The initial output value is the value set in TGRA or TGRC. If the set values of paired

TGRs are identical, the output value does not change when a compare match occurs.

In PWM mode 1, a maximum 8-phase PWM output is possible.

• PWM mode 2

PWM output is generated using one TGR as the cycle register and the others as duty registers. The output specified in

TIOR is performed by means of compare matches. Upon counter clearing by a synchronization register compare

match, the output value of each pin is the initial value set in TIOR. If the set values of the cycle and duty registers are

identical, the output value does not change when a compare match occurs.

In PWM mode 2, a maximum 15-phase PWM output is possible by combined use with synchronous operation.

The correspondence between PWM output pins and registers is shown in table 10-7.

Table 10-7 PWM Output Registers and Output Pins

Note: In PWM mode 2, PWM output is not possible for the TGR register in which the period is set.

Rev.6.00 Oct.28.2004 page 384 of 1016

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