Renesas H8S Series Hardware Manual page 900

BCRH—Bus Control Register H
Bit
Initial value
Read/Write
Rev.6.00 Oct.28.2004 page 872 of 1016
REJ09B0138-0600H
: 7 6
ICIS1 ICIS0 BRSTRM
: 1 1
: R/W R/W
Area 0 Burst ROM Enable
0
1
Idle Cycle Insert 0
Idle cycle not inserted in case of successive external read and external write cycles
0
Idle cycle inserted in case of successive external read and external write cycles
1
Idle Cycle Insert 1
Idle cycle not inserted in case of successive external read cycles in different areas
0
Idle cycle inserted in case of successive external read cycles in different areas
1
H'FED4
5 4 3
BRSTS1 BRSTS0
0 1 0
R/W R/W R/W
RMTS2
Note: When areas selected in DRAM space
Burst Cycle Select 0
0 Max. 4 words in burst access
1 Max. 8 words in burst access
Burst Cycle Select 1
0 Burst cycle comprises 1 state
1 Burst cycle comprises 2 states
Area 0 is basic bus interface
Area 0 is burst ROM interface
Bus Controller
2 1
RMTS2 RMTS1 RMTS0
0 0
R/W R/W
RAM Type Select
RMTS1 RMTS0 Area 5 Area 4 Area 3 Area 2
0 0 0
Normal space
1
Normal space
Normal
1 0
space
1
DRAM space
1 — —
are all 8-bit space, the PF
used as an I/O port, BREQO, or WAIT.
0
0
R/W
DRAM
space
DRAM space
—
pin can be
2